An integrated circuit may contain a depletion mode junction field effect transistor (JFET) which is desired to have a breakdown voltage over 500 volts, a pinch-off voltage less than 10 volts, and an on-state current density greater than 1 microamp per micron of transistor width per volt or drain bias, for example in a startup circuit. It may further be desired to fabricate the integrated circuit using as few photolithographic operations as possible. Simultaneously achieving the desired operating and fabrication goals has been problematic. For example, a depletion mode JFET with a breakdown voltage above 500 volts commonly includes a long drift region. A drift region which is sufficiently doped to provide an on-state current density greater than 1 microamp per micron of transistor width per volt or drain bias may exhibit a pinch-off voltage greater than 20 volts. Conversely, a drift region which is doped lightly enough to provide a pinch-off voltage less than 10 volts may exhibit an on-state current density less than 1 microamp per micron of transistor width per volt of drain bias.